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Time Gated Optical Detector PCB

Time Gated Optical Detector PCB

This project was developed during my internship at ICUBE Laboratory therefore some parts of the project are not disclosed here due to intellectual property reasons. The aims of this post is to share my experience.

Overview

This PCB is designed as a shield for the Cyclone V FPGA DE10nano development board. It is part of a time-gated optical detector system used to measure water pollution through fluorescence detection. The system requires precise timing for pulse generation and detection, which is achieved using the FPGA.

My role in this project was to validate the schematic of the receiver PCB and design test board for each stage of the receiver.

One of the lab setup used to test the receiver PCB

Receiver PCB Design

The receiver PCB is responsible for amplifying the weak fluorescence signals detected by the photodetector. This involves a TIA integrator stage to convert the photocurrent into a voltage signal, followed by sample-and-hold circuits to capture the signal and letting the FPGA process it.

Photodiode Integrator

The first stage of the receiver is a transimpedance amplifier (TIA) integrator. This stage converts the photocurrent generated by the photodiode into a voltage signal. This integrator is reset between each measurement with the TMUX1101 analog switch. This switch has very low switching time (less than 20ns) and low leaking current, which is crucial for the time-gated detection.

Transimpedance Amplifier (TIA) stage on the receiver PCB (Not the final version)

Sample-and-Hold Circuits

The sample-and-hold circuits are used to capture the voltage signal from the integrator to allow the FPGA to convert it using its onboard ADC. This stage uses OPA615, which is often used in video applications.

Sample-and-Hold stage on the receiver PCB (Not the final version)

Test Boards

To validate the design of each stage of the receiver PCB, I designed separate test boards for the TIA integrator and the sample-and-hold circuits. These test boards allowed me to characterize the performance of each stages individually before integrating them into the final receiver PCB.

Sample-and-Hold Test Board

To test the sample-and-hold stage, I designed a dedicated PCB that includes the OPA615 and the necessary components. This board allowed me to evaluate the behavior of the sample-and-hold circuit, including its acquisition time and droop rate. Note that the PCB shown below is intended to be built using isolation milling, which means I cannot use vias.

Sample-and-Hold test board layout

Isolation Milling

Isolation milling is a PCB manufacturing technique in which the copper around the traces is removed, leaving only the traces and pads. This method is particularly useful for prototyping and small production runs, as it enables quick and cost-effective PCB fabrication without the need for chemical etching. With this process, I can design a PCB in the morning, mill it right afterward, take a lunch break, and have it ready for testing in the afternoon.

Opa858 test board after isolation milling

FPGA Integration

The DE10nano development board from Terasic, embedding a Cyclone V FPGA SoC which contains an Hard Processor System (HPS) based on an ARM Cortex-A9. Typically, Nios II would have been the expected choice for computing tasks, but the HPS was preferred in this case due to its superior performance and ease of programming, being able to run a full Linux OS. Terasic provides a debian-based Linux distribution for the HPS. The difficulty lies in the communication between the FPGA and the HPS, which requires setting up the FPGA design using Intel’s Quartus software and configuring the Linux kernel to support the custom hardware. I had to learn how U-Boot and device trees work and how to modify them to include the new peripherals through Avalon bus. Luckily, we can use GHRD (Golden Hardware Reference Design) to start from a working design.

Screenshot of Qsys showing Memory Mapped I/O

Conclusion

Designing the time-gated optical detector PCB was a challenging yet rewarding experience. It allowed me to deepen my understanding of high-speed analog circuit design, PCB layout techniques, and FPGA integration. The use of isolation milling for prototyping was particularly beneficial, enabling rapid iteration and testing of the designs. Overall, this project has significantly enhanced my skills in both hardware design and embedded systems.

I would like to thank the ICUBE Laboratory for providing me with the opportunity to work on this project and for their support throughout the development process.

I was very happy learn that Intel Quartus Prime take up to hundreds of gigabytes of disk space when installing all the features…

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